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R5F2L3ACBNFP Datasheet(PDF) 87 Page - Renesas Technology Corp |
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R5F2L3ACBNFP Datasheet(HTML) 87 Page - Renesas Technology Corp |
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87 / 848 page ![]() 5. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 51 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5.1 Registers 5.1.1 Processor Mode Register 0 (PM0) Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register. 5.1.2 Reset Source Determination Register (RSTFR) Notes: 1. The CWR bit is set to 0 (cold start-up) after power-on, voltage monitor 0 reset, or exit from power-off mode. This bit remains unchanged at a hardware reset, software reset, or watchdog timer reset. 2. When 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.) 3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is undefined. 4. A hardware reset or an exit from power-off mode is detected. Address 0004h Bit b7b6b5 b4b3b2 b1b0 Symbol —— —— PM03 ——— After Reset 000 000 00 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 PM03 Software reset bit Setting this bit to 1 resets the MCU. When read, the content is 0. R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 — Address 000Bh Bit b7b6b5 b4b3b2 b1b0 Symbol — — — — WDR SWR HWR CWR After Reset X X X X 0 0 X X (Note 1) Bit Symbol Bit Name Function R/W b0 CWR Cold start-up/warm start-up determine flag (2, 3) 0: Cold start-up 1: Warm start-up R/W b1 HWR Hardware reset detect flag (4) 0: Not detected 1: Detected R b2 SWR Software reset detect flag 0: Not detected 1: Detected R b3 WDR Watchdog timer reset detect flag 0: Not detected 1: Detected R b4 — Reserved bits When read, the content is undefined. R b5 — b6 — b7 — |
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