R5F2L3ACBNFP datasheet(95/848 Pages) RENESAS

95 / 848 page

5. Resets

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 59 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.7

Cold Start-Up/Warm Start-Up Determination Function

The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold

start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation.

The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 at a voltage monitor 0 reset or an exit from

power-off mode. When 1 is written to the CWR bit by a program, it is set to 1. This bit remains unchanged at a

hardware reset, software reset, or watchdog timer reset.

The cold start-up/warm stat-up determination function uses voltage monitor 0 reset.

To set the bits associated with voltage monitor 0 reset, follow Table 6.3 Procedure for Setting Bits Associated

with Voltage Monitor 0 Reset.

Figure 5.8 shows an Operating Example of Cold Start-Up/Warm Start-Up Function

Figure 5.8

Operating Example of Cold Start-Up/Warm Start-Up Function

5.8

Reset Source Determination Function

The RSTFR register can be used to detect whether a hardware reset, software reset, or watchdog timer reset has

occurred.

If a hardware reset or an exit from power-off mode occurs, the HWR bit is set to 1 (detected).

If a software reset occurs, the SWR bit is set to 1 (detected).

If a watchdog timer reset occurs, the WDR bit is set to 1 (detected).

Set to 1 by

a program.

Vdet0

CWR bit in RSTFR register

Voltage monitor 0 reset

VCC

Set to 1 by

a program.

The above applies when the digital filter is not used.

R5F2L3ACBNFP Datasheet(PDF) 95 Page - Renesas Technology Corp