ATA5425-PLSW datasheet(37/100 Pages) ATMEL

37 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low,

T4 = Low or T5 = Low or the voltage at pin VAUX V

VAUX > 3.5V (typically), the control registers

are in the default state.

Figure 7-1.

7.2

TX/RX Data Buffer

The TX/RX data buffer is used to handle the data transfer during RX and TX operations.

IR1

IR0

OPM1 OPM0

Control Register 1 (ADR 0)

Control Register 2 (ADR 1)

Control Register 3 (ADR 2)

Control Register 4 (ADR 3)

Control Register 5 (ADR 4)

Control Register 6 (ADR 5)

Status Register (ADR 8)

AVCC

_EN

MODE

TX/RX Data Buffer:

× 8 Bit

LSB

MSB

FR3

FR2

FR0

FR1

FR6

FR5

FR4

MODE

FR9

FR8

XLim

XSleep

FR7

FR12

FR11

FR10

VSOUT

_EN

CLK_

ST2

ST1

ST5

ST4

ST3

Power_

Low_

Batt

P_On

_Aux

Sleep

ASK/

NFSK

Lim_

min5

Lim_

min3

Lim_

min0

Lim_

min1

Lim_

min2

Lim_

min4

BitChk

Lim_

max5

Lim_

max3

Lim_

max0

Lim_

max1

Lim_

max2

Lim_

max4

Baud

ATA5425-PLSW Datasheet(PDF) 37 Page - ATMEL Corporation

ATA5425-PLSW Datasheet(HTML) 37 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL