ATA5425-PLSW datasheet(51/100 Pages) ATMEL

51 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

8.8

4-wire Serial Interface

The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial

Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received

bit by bit in synchronization with the serial clock.

Note:

If the output level on pin N_RESET is low, no data communication with the microcontroller is

possible.

When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high

impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX

data stream is available on pin SDO_TMDO.

Figure 8-7.

Serial Timing

Table 8-1.

Command Structure

Command

MSB

LSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read TX/RX data buffer

Write TX/RX data buffer

Read control/status register

Write control register

OFF command

XXX

Delete IRQ

Not used

XXX

Not used

XXX

MSB

MSB-1

LSB

MSB

MSB-1

SCK

SDO_TMDO

SDI_TMDI

CS_disable

SCK_setup2

SCK_hold

SCK_setup1

Cycle

X can be either V

iL or ViH

CS_setup

Out_enable

Out_delay

Setup

Hold

Out_disable

ATA5425-PLSW Datasheet(PDF) 51 Page - ATMEL Corporation

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