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ATA5425-PLSW Datasheet(PDF) 38 Page - ATMEL Corporation |
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ATA5425-PLSW Datasheet(HTML) 38 Page - ATMEL Corporation |
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38 / 100 page ![]() 38 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 7.3 Control Register To use the transceiver in different applications, it can be configured by a connected microcon- troller via the 4-wire serial interface. 7.3.1 Control Register 1 (ADR 0) Table 7-1. Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode) IR1 IR0 Function (RX Mode) 00 Pin IRQ is set to “1” if 4 received bytes are in the TX/RX data buffer or a receiving error occurred 01 Pin IRQ is set to “1” if 8 received bytes are in the TX/RX data buffer or a receiving error occurred 10 Pin IRQ is set to “1” if 12 received bytes are in the TX/RX data buffer or a receiving error occurred (default) 1 1 Pin IRQ is set to “1” if a receiving error occurred Table 7-2. Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode) IR1 IR0 Function (TX Mode) 0 0 Pin IRQ is set to “1” if 4 bytes remain in the TX/RX data buffer or the TX data buffer is empty 0 1 Pin IRQ is set to “1” if 8 bytes remain in the TX/RX data buffer or the TX data buffer is empty 10 Pin IRQ is set to “1” if 12 bytes remain in the TX/RX data buffer or the TX data buffer is empty (default) 1 1 Pin IRQ is set to “1” if the TX data buffer is empty Table 7-3. Control Register 1 (Function of Bit 5) AVCC_EN Function 0 (default) 1 Enables AVCC, if the ATA5423/ATA5425 is in AUX mode Table 7-4. Control Register 1 (Function of Bit 4) FS Function (RX Mode, TX Mode) 0 Selected frequency 345/433/868/915 MHz (default) 1 Selected frequency 315 MHz Table 7-5. Control Register 1 (Function of Bit 2 and Bit 1) OPM1 OPM0 Function 0 0 IDLE mode (default) 0 1 TX mode 1 0 RX polling mode 11 RX mode |
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