ATA5425-PLSW datasheet(62/100 Pages) ATMEL

62 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

9.2

TX Operation

The transceiver is set to TX operation by using the bits OPM0 and OPM1 in the control

Before activating TX mode, the TX parameters (bit rate, modulation scheme, etc.) must be

selected as illustrated in Figure 9-11 on page 63. The bit rate depends on Baud 0 and Baud 1 in

control register 6, Lim_min0 to Lim_min5 in control register 5 and XLIM in control register 4 (see

section “Control Register” on page 38). The modulation is selected with ASK/_NFSK in control

Manchester modulator is disabled and pattern mode is active (NRZ, see Table 9-5 on page 65).

After the transceiver is set to TX mode, the start-up mode is active and the PLL is enabled. If the

PLL is locked, the TX mode is active.

If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire

serial interface. After the first byte is in the buffer and the TX mode is active, the transceiver

starts transmitting automatically (beginning with the MSB). While transmitting it is always possi-

ble to load new data in the TX/RX data buffer. To prevent a buffer overflow or interruptions

during transmitting, the user must ensure that data is loaded at the same speed as it is

transmitted.

There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver

Configuration” on page 49). If a byte is loaded, the counter is incremented, if a byte is transmit-

ted, the counter is decremented. The counter value is available via the 4-wire serial interface. An

IRQ is issued if the counter (while counting down) reaches the value defined by the control bits

IR0 and IR1 in control register 1.

Note:

Writing to the control register 1, 4, 5 or 6 during TX mode resets the TX/RX data buffer and the

counter which indicates the number of bytes to be transmitted.

If T_Mode in control register 1 is set to “1”, the transceiver is in TX transparent mode. In this

mode the TX/RX data buffer is disabled and the TX data stream must be applied on pin

SDI_TMDI. Figure 9-11 on page 63 illustrates the flow chart of the TX transparent mode.

Table 9-4.

Control Register 1

OPM1

OPM0

Function

TX mode

ATA5425-PLSW Datasheet(PDF) 62 Page - ATMEL Corporation