ATA5425-PLSW datasheet(60/100 Pages) ATMEL

60 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX

data buffer byte by byte. The start bit is part of the first data byte and must be different from the

bits of the preburst. If the preburst consists of a sequence of “00000...”, the start bit must be a

“1”. If the preburst consists of a sequence of “11111...”, the start bit must be a “0”.

If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data

buffer control logic overwrites the bytes already stored in the TX/RX data buffer. Therefore, it is

very important to ensure that the data is read in time so that no buffer overflow occurs (see Fig-

ure 8-1 on page 49). There is a counter that indicates the number of received bytes in the TX/RX

data buffer (see section “Transceiver Configuration” on page 49). If a byte is transferred to the

microcontroller, the counter is decremented; if a byte is received, the counter is incremented.

The counter value is available via the 4-wire serial interface.

An interrupt is issued if the counter (while counting up) reaches the value defined by the control

bits IR0 and IR1 in control register 1.

Figure 9-9.

Receiving Mode (TMODE = 0)

If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver

is set back to the start-up mode (see Figure 9-1 on page 54, Figure 9-2 on page 55 and

Figure 9-10 on page 61).

Bit error:

a) t

ee < TLim_min or TLim_max < tee < TLim_min_2T or tee > TLim_max_2T

b) Logical error (no edge detected in the bit center)

Note:

The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus, it is not avail-

able via the 4

-wire serial interface.

Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer con-

trol logic and the counter which indicates the number of received bytes. If the bits OPM0 and

OPM1 are still “1” after writing to a control register, the transceiver changes to the start-up mode

(start-up signal processing).

Demod_Out

Bit check ok

Preburst

Byte 2

LSB

Readable via 4-wire serial interface

TX/RX Data Buffer

MSB

Byte 1

Start

bit

'0' '0' '0' '0' '0' '0' '0' '0' '0' '1'

'1'

'0'

'0' '0' '0' '0'

Byte 14, Byte 30, ...

Byte 13, Byte 29, ...

Byte 10, Byte 26, ...

Byte 9, Byte 25, ...

Byte 8, Byte 24, ...

Byte 3, Byte 19, ...

Byte 1, Byte 17, ...

Byte 2, Byte 18, ...

Byte 4, Byte 20, ...

Byte 5, Byte 21, ...

Byte 6, Byte 22, ...

Byte 7, Byte 23, ...

Byte 11, Byte 27, ...

Byte 12, Byte 28, ...

Byte 16, Byte 32, ...

Byte 15, Byte 31, ...

'0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'

Bit-check mode

Receiving mode

Byte 3

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