ATA5425-PLSW datasheet(46/100 Pages) ATMEL

46 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.6

Pin PWR_ON

To switch the transceiver from OFF to IDLE mode, pin PWR_ON must be set to “1” (minimum

0.8

× V

VS2) for at least TPWR_ON (see Figure 7-4). The transceiver recognizes the positive edge,

sets pin N_RESET to low, and switches on DVCC, AVCC and the power supply for external

devices VSOUT.

If V

DVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and

sets the status bit Power_On to “1” and an interrupt is issued (T

PWR_ON_IRQ_1).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if V

VSOUT exceeds 2.38V

(typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, AUX, RX, RX_Polling, TX), a positive edge on pin

PWR_ON sets Power_On to “1” (after T

PWR_ON_IRQ_2). The state transition Power_On 0 →1 gen-

erates an interrupt. If Power_On is still “1” during the positive edge on pin PWR_ON no interrupt

is issued. Power_On and the interrupt are deleted after reading the status register.

During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”.

Note:

It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to “0”. If pin

PWR_ON is not used, it must be connected to GND.

Figure 7-4.

Timing Pin PWR_ON, Status Bit Power_On

Power_ON

(Status register)

IRQ

CLK

N_RESET

DVCC, AVCC

VSOUT

PWR_ON

OFF

Mode

IDLE

Mode

IDLE, AUX, RX, RX Polling, TX

Mode

PWR_ON > TPWR_ON_IRQ_2

PWR_ON > TPWR_ON_IRQ_1

PWR_ON_IRQ_2

PWR_ON_IRQ_1

1.5V (typ)

Thres_2 = 2.38V (typ)

Thres_1 = 2.V

(typ)

ATA5425-PLSW Datasheet(PDF) 46 Page - ATMEL Corporation

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