TS80C52X2-VCKB datasheet(18/54 Pages) TEMIC

18 / 54 page

Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

6.4 TS80C52X2 Serial I/O Port

The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

Framing error detection

Automatic address recognition

6.4.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing

bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).

Figure 6. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.

RB8

TB8

REN

SM2

SM1

SM0/FE

IDL

GF0

GF1

POF

SMOD0

SMOD1

To UART framing error control

SM0 to UART mode control (SMOD = 0)

Set FE bit if stop bit is 0 (framing error) (SMOD = 1)

SCON (98h)

PCON (87h)

TS80C52X2-VCKB Datasheet(PDF) 18 Page - TEMIC Semiconductors