M68HC08 datasheet(80/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

Likewise, when DSTG[4:0] is %11111, the ring operates at 25 stage delays for 31

of 32 cycles and at 23 stage delays for one of 32 cycles. When DSTG[7:5] is %111,

similar results are achieved by including a variable divide-by-two, so the ring

operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two

for an effective 34 stage delays, for the remainder of the cycles. Adjusting the

DSTG[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period.

This corresponds to the minimum size correction made by the DLF, and the

inherent, long-term quantization error in the output frequency.

6.4.5 Switching Internal Clock Frequencies

The frequency of the internal clock (ICLK) may need to be changed for some

applications. For example, if the reset condition does not provide the correct

frequency, or if the clock is slowed down for a low-power mode (or sped up after a

low-power mode), the frequency must be changed by programming the internal

clock multiplier factor (N). The frequency of ICLK is N times the frequency of

IBASE, which is 307.2 kHz

±25 percent.

Before switching frequencies by changing the N value, the clock monitor must be

disabled. This is because when N is changed, the frequency of the low-frequency

base clock (IBASE) will change proportionally until the digital loop filter has

corrected the error. Since the clock monitor uses IBASE, it could erroneously

detect an inactive clock. The clock monitor cannot be re-enabled until the internal

clock is stable again (ICGS is set).

NOTE:

There is no hardware mechanism to prevent changing bus frequency dynamically.

Be careful when changing bus frequency and consider the impact on the system.

This flow is an example of how to change the clock frequency:

Verify there is no clock monitor interrupt by reading the CMF bit.

Turn off the clock monitor.

If desired, switch to the external clock (see 6.4.1 Switching Clock

Sources).

Change the value of N.

Switch back to internal (see 6.4.1 Switching Clock Sources), if desired.

Turn on the clock monitor (see 6.4.2 Enabling the Clock Monitor),

if desired.

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