M68HC08 datasheet(89/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

I/O Registers

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

CS — Clock Select Bit

This read/write bit determines which clock will generate the oscillator output

clock (CGMXCLK). This bit can be set when ECGON and ECGS have been set

for at least one bus cycle and can be cleared when ICGON and ICGS have been

set for at least one bus cycle. This bit is forced set when the clock monitor

determines the internal clock (ICLK) is inactive or when ICGON is clear. This bit

is forced clear when the clock monitor determines that the external clock (ECLK)

is inactive, when ECGON is clear, or during reset.

1 = External clock (ECLK) sources CGMXCLK

0 = Internal clock (ICLK) sources CGMXCLK

ICGON — Internal Clock Generator On Bit

This read/write bit enables the internal clock generator. ICGON can be cleared

when the CS bit has been set and the CMON bit has been clear for at least one

bus cycle. ICGON is forced set when the CMON bit is set, the CS bit is clear, or

during reset.

1 = Internal clock generator enabled

0 = Internal clock generator disabled

ICGS — Internal Clock Generator Stable Bit

This read-only bit indicates when the internal clock generator has determined

that the internal clock (ICLK) is within about 5 percent of the desired value. This

bit is forced clear when the clock monitor determines the ICLK is inactive, when

ICGON is clear, when the ICG multiplier factor is written, or during reset.

1 = Internal clock is within 5 percent of the desired value.

0 = Internal clock may not be within 5 percent of the desired value.

ECGON — External Clock Generator On Bit

This read/write bit enables the external clock generator. ECGON can be cleared

when the CS and CMON bits have been clear for at least one bus cycle.

ECGON is forced set when the CMON bit or the CS bit is set. ECGON is forced

clear during reset.

1 = External clock generator enabled

0 = External clock generator disabled

ECGS — External Clock Generator Stable Bit

This read-only bit indicates when at least 4096 external clock (ECLK) cycles

have elapsed since the external clock generator was enabled. This is not an

assurance of the stability of ECLK but is meant to provide a startup delay. This

bit is forced clear when the clock monitor determines ECLK is inactive, when

ECGON is clear, or during reset.

1 = 4096 ECLK cycles have elapsed since ECGON was set.

0 = External cock is unstable, inactive, or disabled.

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