M68HC08 datasheet(82/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Data Sheet

MC68HC908RF2 — Rev. 4.0

Internal Clock Generator Module (ICG)

MOTOROLA

6.4.6.2 Settling to Within 5 Percent

Once the clock period is within 15 percent of the desired clock period, the filter

starts making smaller adjustments. When between 15 percent and 5 percent error,

each correction will adjust the clock period between 1.61 percent and 2.94 percent.

In this mode, a maximum of eight corrections will be required to get to less than 5

percent error. Since the clock period is relatively close to desired, each correction

takes approximately the same period of time, or 4*tIBASE. At this point, the internal

clock stable bit (ICGS) will be set and the clock frequency is usable, although the

error will be as high as 5 percent. The total time to this point is:

6.4.6.3 Total Settling Time

Once the clock period is within 5 percent of the desired clock period, the filter starts

making minimum adjustments. In this mode, each correction will adjust the

frequency between 0.202 percent and 0.368 percent. A maximum of 24 corrections

will be required to get to the minimum error. Each correction takes approximately

the same period of time or 4*tIBASE. Added to the corrections for 15 percent to 5

percent, this makes 32 corrections (128*tIBASE) to get from 15 percent to the

minimum error. The total time to the minimum error is:

The equations for t15, t5, and ttot are dependent on the actual initial and final clock

periods t1 and t2, not the nominal. This means the variability in the ICLK frequency

due to process, temperature, and voltage must be considered. Additionally, other

process factors and noise can affect the actual tolerances of the points at which the

filter changes modes. This means a worst case adjustment of up to 35 percent

(ICLK clock period tolerance plus 10 percent) must be added. This adjustment can

be reduced with trimming. Table 6-4 shows some typical values for settling time.

abs 44N t

–

()

[] 32t

IBASE

Table 6-4. Typical Settling Time Examples

t15

ttot

1/ (6.45 MHz)

1/ (25.8 MHz)

430

µs

535

µs

850

µs

1/ (25.8 MHz)

1/ (6.45 MHz)

107

µs

212

µs

525

µs

1/ (25.8 MHz)

1/ (307.2 kHz)

141

µs

246

µs

560

µs

1/ (307.2 kHz)

1/ (25.8 MHz)

11.9 ms

12.0 ms

12.3 ms

tot

abs 44N t

–

()

[] 128t

IBASE

Freescale Semiconductor, Inc.

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