M68HC08 datasheet(83/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

Usage Notes

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

6.4.7 Improving Settling Time

The settling time of the internal clock generator can be vastly improved if an

external clock source can be used during the settling time. When the internal clock

generator is disabled (ICGON is low), the DDIV[3:0] and DSTG[7:0] bits can be

written. Then, when the internal clock generator is re-enabled, the clock period will

automatically start at the point written in the DDIV and DSTG bits.

Since a change in the DDIV and DSTG bits only cause a change in the clock period

relative to the starting point, the starting point must first be captured. The initial

clock period can be expressed as in the next example, where tX is a process,

temperature, and voltage dependent constant and DDIV1 and DSTG1 are the

values of DDIV and DSTG when operating at t1.

Finding the new values for DDIV and DSTG is easy if the new clock period is a

binary multiple or fraction of the original. In this case, DSTG is unchanged and

DDIV2 is DDIV1 + log2(t2/t1).

If the new clock period is not a binary multiple or fraction of the original, both DSTG

and DDIV may need to change according to these equations:

If DSTG2 is greater than 255:

The software required to do this is relatively simple, since most of the math can be

done before coding because the initial and final clock periods are known. An

example of how to code this in assembly code is shown in Figure 6-9. This

example is for illustrative purposes only and does not represent a valid syntax for

any particular assembler.

DDIV1

DSTG1

⋅⋅

DVFACT

int

⁄

()

log

()

log

---------------------------

DDIV2

DDIV1

DVFACT

DSFACT

⁄

()

DDIV2

DDIV1

–

()

----------------------------------------------------

DSTG2

DSFACT DSTG1

⋅

DDIV2

DSTG2

---------------------

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