M68HC08 datasheet(91/188 Pages) FREESCALE

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Internal Clock Generator Module (ICG)

I/O Registers

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

6.7.4 ICG DCO Divider Register

DDIV3–DDIV0 — ICG DCO Divider Control Bits

These bits indicate the number of divide-by-twos (DDIV) that follow the digitally

controlled oscillator. Incrementing DDIV will add another divide-by-two,

doubling the period (halving the frequency). Decrementing has the opposite

effect. DDIV cannot be written when ICGON is set to prevent inadvertent

frequency shifting. When ICGON is set, DDIV is controlled by the digital loop

filter. The range of valid values for DDIV is from $0 to $9. Values of $A–$F are

interpreted the same as $9. Since the DCO is active during reset, reset has no

effect on DSTG and the value may vary.

6.7.5 ICG DCO Stage Register

DSTG7–DSTG0 — ICG DCO Stage Control Bits

These bits indicate the number of stages DSTG (above the minimum) in the

digitally controlled oscillator. The total number of stages is approximately equal

to $1FF, so changing DSTG from $00 to $FF will approximately double the

period. Incrementing DSTG will increase the period (decrease the frequency) by

0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG

cannot be written when ICGON is set to prevent inadvertent frequency shifting.

When ICGON is set, DSTG is controlled by the digital loop filter. Since the DCO

is active during reset, reset has no effect on DSTG and the value may vary.

Address: $0039

Bit 7

654321

Bit 0

Read:

RRRR

DDIV3

DDIV2

DDIV1

DDIV0

Write:

Reset:

0000

UUUU

= Reserved

U = Unaffected

Figure 6-14. ICG DCO Divider Register (ICGDVR)

Address: $003A

Bit 7

654321

Bit 0

Read:

DSTG7

DSTG6

DSTG5

DSTG4

DSTG3

DSTG2

DSTG1

DSTG0

Write:

Reset:

Unaffected by reset

Figure 6-15. ICG DCO Stage Register (ICGDSR)

Freescale Semiconductor, Inc.

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