TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

36

POST OFFICE BOX 1443

NO

TMS320C44 - 50

TMS320C44 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

1

tc(WORD)‡§

Cycle time, word transfer (4 bytes = 1 word)

1.5P + 7

2.5P + 170

1.5P + 7

2.5P + 170

ns

2

td(CRDYL-CSL)W‡

Delay time, CRDYx low to CSTRBx low between

back-to-back write cycles

1.5P + 7

2.5P + 28

1.5P + 7

2.5P + 28

ns

† For these timing values, it is assumed that the ’C4x receiving data is ready to receive data. Line propagation delay is not considered.

‡ This value is characterized but not tested.

§ tc(WORD) max = 2.5P + 28 ns + the maximum summed values of 4 × td(CSL-CRDYL)R, 3 × td(CRDYL-CSH), 3 × td(CSH-CRDYH)R, and

3

× td(CRDYH-CSL)W as seen in Figure 24. This timing assumes two ’C4xs are connected.

NOTE 13: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C44, timings can be longer. No

restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB

width restriction section of the

TMS320C4x User’s Guide (literature number SPRU063B).

CREQx

CACKx

CSTRBx

CxDx

CRDYx

1

2

Undef.

B0

B1

B2

B3

B0¶

= When signal is an input (clear = when signal is an output).

¶ Begins byte 0 of the next word.

NOTE A: For correct operation during token exchange, the two communicating ’C4xs must have CLKIN frequencies within a factor of 2 of each

other (in other words, at most, one of the ’C4xs can be twice as fast as the other).