(L)PAGEx

(see Note D)

Control Signals

(see Note D)

(L)Dx

(see Note C)

RESET

(see Notes A and B)

1

2.1

4.1

6

7

8

3

2.2

4.2

7

CLKIN

H1

H3

(L)Ax

see Note C)

IACK

Asynchronous Reset

Signals (see Note E)

Asynchronous Reset

Signals (see Note A)

Ten H1 Clock Cycles

5

9

9

10

CDIRx

(see Note F)

12

11

CDIRy

(see Note F)

NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy

(where x = 1 or 2 and y = 4 or 5).

B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise,

an additional delay of one clock cycle can occur.

C. For this diagram, (L)Dx includes D31 – D0, LD31 – LD0, and CxD7 – CxD0; (L)Ax includes LA(23 – 0) and A(23 – 0).

D. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3 – (L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.

E. Asynchronous reset signals that go into the high-impedance state after RESET goes low include TCLK0, TCLK1, IIOF3 – IIOF0, and the communication-port control

signals CREQx, CACKy, CSTRBy, and CRDYx (where x = 1 or 2, and y = 4 or 5). At reset, ports 1 and 2 become outputs, and ports 4 and 5 become inputs.

F. x = 1 or 2 and y = 4 or 5

Figure 20. RESET Timing