TMS320C44 datasheet(14/42 Pages) TI

14 / 42 page

TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA coprocessor

The DMA coprocessor allows concurrent I / O and CPU processing for the highest sustained CPU performance.

The key features of the DMA coprocessor are:

D Link pointers to allow DMA channels to autoinitialize without CPU intervention

D Parallel CPU operation and DMA transfers

D Six DMA channels to support memory-to-memory data transfers

D Split-mode operation which doubles the available channels to twelve when data transfers to and from a

communication port are required

communication ports

The ’320C44 contains four identical high-speed communication ports, each of which provides a

bidirectional-communication interface to other ’C4x devices and external peripherals. The key features of the

communication ports are:

D Direct interprocessor communication and processor I/O

D 20M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface

D Port direction pin (CDIR) to ease interfacing

D Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O

D Automatic arbitration and handshaking for direct processor-to-processor connection

communication-port direction pin

A port-direction pin (CDIR1, CDIR2, CDIR4, CDIR5) is available for each ’C44 communication port. When the

communication port is in the output mode, CDIRx is driven low. When the communication port is in the input

mode, CDIRx is driven high. The truth table for two ’320C44 devices is shown in Table 1. Communication

port 1 of CPUA is connected to communication port 4 of CPUB.

Table 1. Truth Table for Two ’320C44 Devices

CDIR1

CDIR4

DESCRIPTION

Token error

CPUA is configured to transmit to CPUB.

CPUB is configured to transmit to CPUA .

Token exchange overlap, if > 1H then token error

communication-port-software reset

The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back

values to its communication-port software-reset address as specified in Table 2. This software reset flushes any

word or byte already present in the FIFOs, but it does not affect the status of the communication-port pins.

Table 2. Communication-Port Software-Reset Address

COMMUNICATION PORT

SOFTWARE-RESET ADDRESS

0x0100053

0x0100063

0x0100083

0x0100093

TMS320C44 Datasheet(PDF) 14 Page - Texas Instruments

TMS320C44 Datasheet(HTML) 14 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL