TMS320C44 datasheet(22/42 Pages) TI

22 / 42 page

TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 8, Figure 10, and

Figure 11)

TMS320C44- 50

TMS320C44- 60

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

td(H1L - SL)

Delay time, H1 low to (L)STRBx low

0†

td(H1L - SH)

Delay time, H1 low to (L)STRBx high

0†

td(H1H - RWL)

Delay time, H1 high to (L)R / Wx low

0†

td(H1L - A)

Delay time, H1 low to (L)Ax valid

0†

tsu(D-H1L)R

Setup time, (L)Dx valid before H1 low (read)

th(H1L-D)R

Hold time, (L)Dx after H1 low (read)

tsu(RDY-H1L)

Setup time, (L)RDYx valid before H1 low

20‡

18†

th(H1L-RDY)

Hold time, (L)RDYx after H1 low

8.1

td(H1L - ST)

Delay time, H1 low to (L)STAT3 – (L)STAT0 valid

td(H1H-RWH)W

Delay time, H1 high to (L)R / Wx high (write)

0†

tv(H1L-D)W

Valid time, (L)Dx after H1 low (write)

th(H1H-D)W

Hold time, (L)Dx after H1 high (write)

td(H1H - A)

Delay time, H1 high to address valid on back-to-back write cycles

† This value is specified by design but not tested.

‡ If this setup time is not met, the read / write operation is not assured.

NOTE 8: For consecutive reads, (L)R / Wx stays high and (L)STRBx stays low.

TMS320C44 Datasheet(PDF) 22 Page - Texas Instruments

TMS320C44 Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL