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TMS320VC549 Datasheet(PDF) 58 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 111 page ![]() TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics and operating conditions — ’C541, ’C542 (continued) electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage‡ IOH = –300 µA 2.4 V VOL Low-level output voltage‡ IOL = 2 mA 0.6 V IIZ Input current in high impedance VDD = MAX, VI = VSS to VDD –20 20 µA TRST With internal pulldown –10 800 µA It t HPIENA With internal pulldown, RS = 0 –10 400 II Input current (VI =VSS to VDD) TMS, TCK, TDI, HPI|| With internal pullups –500 10 A II (VI = VSS to VDD) D[15:0], HD[7:0] Bus holders enabled, VDD = MAXk –150 250 µA All other input-only pins –10 10 IDDC Supply current, core CPU VDD = 5 V, fx = 40 MHz,§ TC = 25°C 47¶ mA IDDP Supply current, pins VDD = 5 V, fx = 40 MHz,§ TC = 25°C 18# mA IDD Supply current standby IDLE2 PLL × 1 mode, 40 MHz input 4 mA IDD Supply current, standby IDLE3 Divide-by-two mode, CLKIN stopped 5 µA Ci Input capacitance 10 pF Co Output capacitance 10 pF † All typical values are at VDD = 5 V, TC = 25°C. ‡ All input and output voltage levels except RS, INT0 – INT3, NMI, CNT, X2/CLKIN, CLKMD0 – CLKMD3 are TTL-compatible. § Clock mode: PLL × 1 with external source ¶ This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. # This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164). || HPI input signals except for HPIENA. kVIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX) |
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