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TMS320VC549 Datasheet(PDF) 94 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 buffered serial port transmit timing of external frames switching characteristics over recommended operating conditions for buffered serial port transmit of external frames (see Figure 36) PARAMETER ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX td(BDX) Delay time, BDX valid after BCLKX rising 18 18 ns tdis(BDX) Disable time, BDX after BCLKX rising 4 6 4 6 ns tdis(BDX)pcm Disable time, PCM mode, BDX after BCLKX rising 6 6 ns ten(BDX)pcm Enable time, PCM mode, BDX after BCLKX rising 8 8 ns th(BDX) Hold time, BDX valid after BCLKX rising 4 2 ns timing requirements for buffered serial port transmit of external frames (see Figure 36) ’C54x-40 ’LC54x-40 ’54x-50 ’54x-66 UNIT MIN MAX MIN MAX UNIT tc(SCK) Cycle time, serial port clock 25 † 20 † ns tf(SCK) Fall time, serial port clock 4 4 ns tr(SCK) Rise time, serial port clock 4 4 ns tw(SCK) Pulse duration, serial port clock low/high 8.5 6 ns th(BFSX) Hold time, BFSX after CLKX falling edge (see Notes 3 and 4) 6 tc(SCK) – 6‡ 6 tc(SCK) – 6‡ ns tsu(BFSX) Setup time, FSX before CLKX falling edge (see Notes 3 and 4) 6 6 ns † The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency of 0 Hz but tested at a much higher frequency to minimize test time. ‡ If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX). After falling edge of the BFSX, data will be shifted out on the BDX pin. NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX. 4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0. |
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