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TMS320VC549 Datasheet(PDF) 84 Page - Texas Instruments

Part # TMS320VC549
Description  FIXED-POINT DIGITAL SIGNAL PROCESSORS
PDF  111 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC549 Datasheet(HTML) 84 Page - Texas Instruments

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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
84
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
HOLD and HOLDA timing
switching characteristics over recommended operating conditions for memory control signals
and HOLDA [H = 0.5 tc(CO)] (see Figure 25)
PARAMETER
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
MAX
MIN
MAX
tdis(CLKL-A)
Disable time, CLKOUT low to address, PS, DS, IS high impedance
5
5
ns
tdis(CLKL-RW)
Disable time, CLKOUT low to R/W high impedance
5
5
ns
tdis(CLKL-S)
Disable time, CLKOUT low to MSTRB, IOSTRB high
impedance
5
5
ns
ten(CLKL-A)
Enable time, CLKOUT low to address, PS, DS, IS
2H + 5
2H + 5
ns
ten(CLKL-RW)
Enable time, CLKOUT low to R/W enabled
2H + 5
2H + 5
ns
ten(CLKL-S)
Enable time, CLKOUT low to MSTRB, IOSTRB enabled
2H + 5
2H + 5
ns
t
Valid time, HOLDA low after CLKOUT low
– 2
5
0
5
ns
tv(HOLDA)
Valid time, HOLDA high after CLKOUT low
– 2
5
– 2
3
ns
tw(HOLDA)
Pulse duration, HOLDA low duration
2H –3
2H –3
ns
timing requirements for HOLD [H = 0.5 tc(CO)] (see Figure 25)
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
MAX
MIN
MAX
tw(HOLD)
Pulse duration, HOLD low duration
4H + 10
4H + 10
ns
tsu(HOLD)
Setup time, HOLD before CLKOUT low
10
10
ns



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