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TMS320VC549 Datasheet(PDF) 69 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 69 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 16) ’LC542-40 ’LC543-40 ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX MIN MAX MIN MAX UNIT ta(A)M Access time, read data access from address valid 2H–12 2H–10 2H–10 2H–10 ns ta(MSTRBL) Access time, read data access from MSTRB low 2H–12 2H–10 2H–10 2H–10 ns tsu(D)R Setup time, read data before CLKOUT low 7 5 5 5 ns th(D)R Hold time, read data after CLKOUT low 0 0 0 2 ns th(A-D)R Hold time, read data after address invalid 0 0 0 1 ns th(D)MSTRBH Hold time, read data after MSTRB high 0 0 0 0 ns † Address, PS, and DS timings are all included in timings referenced as address. ‡ See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance. |
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