TMS320VC549 datasheet(99/111 Pages) TI

99 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial-port transmit timing in TDM mode

switching characteristics over recommended operating conditions for serial-port transmit in TDM

mode [H = 0.5tc(CO)] (see Figure 39)

PARAMETER

’542

’543

’C54x-40

’LC54x-40

’LC54x-50

UNIT

MIN

MAX

MIN

MAX

th(TCH-TDV)

Hold time, TDAT / TADD valid after TCLK rising edge, TCLK external

th(TCH-TDV)

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal

– 5

Delay time, TFRM valid after TCLK rising edge TCLK ext†

H – 3

3H + 22

H – 3

3H + 22

td(TCH-TFV)

Delay time, TFRM valid after TCLK rising edge, TCLK int†

H – 3

3H + 12

H – 3

3H + 12

td(TC TDV)

Delay time, TCLK to valid TDAT/TADD, TCLK ext

td(TC-TDV)

Delay time, TCLK to valid TDAT/TADD, TCLK int

† TFRM timing and waveforms shown in Figure 39 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is

illustrated in the receive timing diagram in Figure 38.

switching characteristics over recommended operating conditions for serial-port transmit in TDM

mode [H = 0.5tc(CO)] (see Figure 39)

PARAMETER

’54x-66

UNIT

PARAMETER

MIN

MAX

UNIT

th(TCH-TDV)

Hold time, TDAT / TADD valid after TCLK rising edge, TCLK external

th(TCH-TDV)

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal

Delay time, TFRM valid after TCLK rising edge, TCLK ext†

H – 3

3H+22

td(TCH-TFV)

Delay time, TFRM valid after TCLK rising edge, TCLK int†

H – 3

3H+12

td(TC TDV)

Delay time, TCLK to valid TDAT/TADD, TCLK ext

td(TC-TDV)

Delay time, TCLK to valid TDAT/TADD, TCLK int

† TFRM timing and waveforms shown in Figure 39 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is

illustrated in the receive timing diagram in Figure 38.

TMS320VC549 Datasheet(PDF) 99 Page - Texas Instruments

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