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IMX35 Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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IMX35 Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 148 page  i.MX35 Applications Processors for Automotive Products, Rev. 6 Freescale Semiconductor 53 NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Figure 31. DDR2 SDRAM Basic Timing Parameters Table 36. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD16 CKE output delay time tCKS 1.8 — ns Table 37. DDR2 SDRAM Timing Parameter Table ID PARAMETER Symbol DDR2-400 Unit Min Max DDR1 SDRAM clock high-level width tCH 0.45 0.55 tCK DDR2 SDRAM clock low-level width tCL 0.45 0.55 tCK DDR3 SDRAM clock cycle time tCK 7.0 8.0 ns DDR4 CS, RAS, CAS, CKE, WE setup time tIS1 0.35 — ns SDCLK WE ADDR ROW/BA COL/BA CS CAS RAS DDR1 DDR3 DDR2 DDR4 DDR4 DDR4 DDR5 DDR5 DDR5 DDR5 DDR6 DDR7 SDCLK CKE DDR4 DDR4 |
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