IMX35 datasheet(17/148 Pages) FREESCALE

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i.MX35 Applications Processors for Automotive Products, Rev. 6

Freescale Semiconductor

4.3

Supply Power-Up/Power-Down Requirements and Restrictions

This section provides power-up and power-down sequence guidelines for the i.MX35 processor.

CAUTION

Any i.MX35 board design must comply with the power-up and power-down

sequence guidelines as described in this section to guarantee reliable

operation of the device. Any deviation from these sequences can result in

irreversible damage to the i.MX35 processor (worst-case scenario).

Stop

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is off.

PER PLL is off.

All clocks are gated off.

OSC 24 MHz is on

OSC audio is off

RNGC internal osc is off

1.1

400

µA

2.2

1.2

2.2

Static

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is off.

PER PLL is off.

All clocks are gated off.

OSC 24MHz is on

OSC audio is off

RNGC internal osc is off

820

µA

1.7

µA

Note: Typical column: TA = 25

°C

Note: Maximum column: TA = 85

°C

Table 10. i.MX35 Power Modes (continued)

Power

Mode

Description

QVCC (ARM/L2

Peripheral)

MVDD/PVDD

OSC24M_VDD

OSC_AUDO_VDD

Typ.

Max.

Typ.

Max.

Typ.

Max.

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