IMX35 datasheet(112/148 Pages) FREESCALE

112 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

112

4.9.21

SPDIF Timing

SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by

a clock that is twice the bit rate of the data signal.

Figure 91 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.

SJ11

TCK low to TDO high impedance

—

SJ12

TRST assert time

100

—

SJ13

TRST set-up time to TCK low

—

1 On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency

to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.

2 V

M = mid point voltage

Table 73. SPDIF Timing Parameters

Parameters

Symbol

Timing Parameter Range

Units

Min.

Max.

SPDIFIN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIFOUT output (Load = 50 pf)

•Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIFOUT1 output (Load = 30 pf)

•Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SRCK) period

srckp

40.0

—

SRCK high period

srckph

16.0

—

SRCK low period

srckpl

16.0

—

Modulating Tx clock (STCLK) period

stclkp

40.0

—

STCLK high period

stclkph

16.0

—

STCLK low period

stclkpl

16.0

—

Table 72. SJC Timing Parameters (continued)

Parameter

All Frequencies

Unit

Min.

Max.

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