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IMX35 Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc |
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IMX35 Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 148 page ![]() i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 113 Figure 91. SRCK Timing Figure 92. STCLK Timing 4.9.22 SSI Electrical Specifications This section describes electrical characteristics of the SSI. NOTE • All of the timing for the SSI is given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. • All timing is on AUDMUX signals when SSI is being used for data transfer. • “Tx” and “Rx” refer to the transmit and receive sections of the SSI, respectively. • For internal frame sync operations using the external clock, the FS timing will be the same as that of Tx Data (for example, during AC97 mode of operation). SRCK (Output) VM VM srckp srckph srckpl STCLK (Input) VM VM stclkp stclkph stclkpl |
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