AT90SCR100 datasheet(106/433 Pages) ATMEL

106 / 433 page

106

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 13-12.

16-bit Timer/Counter Block Diagram

13.2.1.1

Registers

The Timer/Counter1 (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg-

ister

(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 107. The Timer/Counter Control Registers (TCCR1A/B/C) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with

the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter1 can be clocked internally, via the prescaler, or by an external clock source

on the T1 pin. The Clock Select logic block controls which clock source and edge the

Timer/Counter uses to increment (or decrement) its value. The Timer/Counter1 is inactive when

no clock source is selected. The output from the Clock Select logic is referred to as the timer

clock (clkTn).

The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun-

ter value at all time. The result of the compare can be used by the Waveform Generator to

Clock Select

Timer/Counter

OCR1A

OCR1B

ICR1

TCNT1

Waveform

Generation

Waveform

Generation

OC1A

OC1B

Noise

Canceler

ICP1

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOV1

(Int.Req.)

OC1A

(Int.Req.)

OC1B

(Int.Req.)

ICF1 (Int.Req.)

TCCR1A

TCCR1B

Edge

Detector

( From Prescaler )

clk

AT90SCR100 Datasheet(PDF) 106 Page - ATMEL Corporation

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