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AT90SCR100 Datasheet(PDF) 126 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 126 Page - ATMEL Corporation |
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126 / 433 page  126 TPR0327AY–SMS–30Jan09 AT90SCR100 Figure 13-24. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) 13.2.10 16-bit Timer/Counter Register Description 13.2.10.1 TCCR1A – Timer/Counter1 Control Register A • Bit 7..6 – COM1A1..0: Compare Output Mode for Channel A • Bit 5..4 – COM1B1..0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec- tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond- ing to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. Table 13-11 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). TOV1(FPWM) and ICF1 (if used as TOP) OCR1x (Update at TOP) TCNT1 (CTC and FPWM) TCNT1 (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCR1x Value New OCR1x Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7654 3 2 1 0 $000080 COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 TCCR1A Read/write R/W R/W R/W R/W R R R/W R/W Initial value 0000 0 0 0 0 0x00 Table 13-11. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 10 Clear OC1A/OC1B on Compare Match (Set output to low level). 11 Set OC1A/OC1B on Compare Match (Set output to high level). |
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