AT90SCR100 datasheet(153/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

advanced by at least one before the processor can read the timer value causing the setting of

the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

13.3.9.3

TIMSK2 – Timer/Counter2 Interrupt Mask Register

• Bit 2 – OCIE2B : Timer/Counter2 Output Compare Match B Interrupt Enable

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Coun-

ter 2 Interrupt Flag Register – TIFR2.

• Bit 1 – OCIE2A : Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Coun-

ter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2 : Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt

Flag Register – TIFR2.

13.3.9.4

TIFR2 – Timer/Counter2 Interrupt Flag Register

• Bit 2 – OCF2B : Output Compare Flag 2 B

The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt

Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 1 – OCF2A : Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

Bit

$000070

OCIE2B

OCIE2A

TOIE2

TIMSK2

Read/write

R/W

Initial value

0x00

Bit

0x17 (0x37)

OCF2B

OCF2A

TOV2

TIFR2

Read/write

R/W

Initial value

0x00

AT90SCR100 Datasheet(PDF) 153 Page - ATMEL Corporation

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