PIC16F1933-ESLASHP datasheet(283/418 Pages) MICROCHIP

283 / 418 page

Preliminary

DS41364A-page 281

PIC16F193X/LF193X

22.3

SPI Mode

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four clock

modes of SPI are supported in both Master and Slave

modes. To accomplish communication, typically three

pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS)

Figure 22-1 shows the block diagram of the MSSP

module when operating in SPI mode.

22.3.1

REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPSTAT)

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 3 (SSPCON3)

• MSSP Data Buffer register (SSPBUF)

• MSSP Address register (SSPADD)

• MSSP Shift register (SSPSR)

(Not directly accessible)

SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

In one SPI master mode, SSPADD can be loaded with

a value used in the Baud Rate Generator. More infor-

mation on the Baud Rate Generator is available in

Section 22.7 “Baud Rate Generator”.

SSPSR is the shift register used for shifting data in and

out. SSPBUF provides indirect access to the SSPSR

bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPBUF together

create a buffered receiver. When SSPSR receives a

complete byte, it is transferred to SSPBUF and the

SSPIF interrupt is set.

During transmission, the SSPBUF is not buffered. A

write to SSPBUF will write to both SSPBUF and

SSPSR.

22.3.2

OPERATIONS

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

SSPSTAT register, and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the write collision detect bit WCOL

of the SSPCON1 register, will be set. User software

must clear the WCOL bit to allow the following write(s)

to the SSPBUF register to complete successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF of the SSPSTAT register, indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur.

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSPSTAT register indicates the

various Status conditions.

PIC16F1933-E/P Datasheet(PDF) 283 Page - Microchip Technology

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