PIC16F1933-ESLASHP datasheet(286/418 Pages) MICROCHIP

286 / 418 page

PIC16F193X/LF193X

DS41364A-page 284

Preliminary

22.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last

bit is latched, the SSPIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSPCON1 register.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCK pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

22.3.6.1

Buffer Overwrite Enable

In SPI daisy-chained configurations only the most

recent byte on the bus is required by the slave. Setting

the BOEN bit of the SSPCON3 register will enable

writes to the SSPBUF register, even if the previous

byte has not been read. Allowing the software to

ignore data that may not apply to it.

22.3.7

SLAVE SELECT SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 0100).

When the SS pin is low, transmission and reception are

enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

FIGURE 22-6:

SLAVE SELECT SYNCRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SS pin

control

enabled

(SSPCON1<3:0>

0100

), the SPI module will reset if the SS

pin is set to VDD.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SS pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPSTAT register must

remain clear.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO

bit 7

bit 6

bit 7

SSPIF

Interrupt

CKE = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7

bit 0

bit 6

SSPBUF to

SSPSR

Shift register SSPSR

and bit count are reset

PIC16F1933-E/P Datasheet(PDF) 286 Page - Microchip Technology

PIC16F1933-E/P Datasheet(HTML) 286 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL