PIC16F1933-ESLASHP datasheet(289/418 Pages) MICROCHIP

289 / 418 page

Preliminary

DS41364A-page 287

PIC16F193X/LF193X

22.4

I2C

MODE

All MSSP I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and 2 interrupt

flags interface the module with the PIC® microcon-

troller and user software. Two pins, SDA and SCL, are

exercised by the module to communicate with other

external I2C devices.

22.4.1

SDA AND SCL PINS

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain. These

pins should be set by the user to inputs by setting the

appropriate TRIS bits.

22.4.2

BYTE FORMAT

All communication in I2C is done in 9-bit segments. A

byte is sent from a Master to a Slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the 8th

falling edge of the SCL line, the device outputting data

on the SDA changes that pin to an input and reads in

an acknowledge value on the next clock pulse.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

22.4.3

DEFINITION OF I2C TERMINOLOGY

There is language and terminology in the description

of I2C communication that have definitions specific to

I2C. That word usage is defined below and may be

used in the rest of this document without explana-

tion.

This table was adapted from the Phillips I2C

specification.

TABLE 22-2:

I2C BUS TERMS

Note: Data is tied to output zero when an I2C mode

is enabled.

TERM

Description

Transmitter

The device which shifts data out

onto the bus.

Receiver

The device which shifts data in

from the bus.

Master

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave

The device addressed by the mas-

ter.

Multi-master

A bus with more than one device

that can initiate data transfers.

Arbitration

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDA and SCL lines are

high.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPADD.

Write Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision

Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

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