PIC16F1933-ESLASHP datasheet(293/418 Pages) MICROCHIP

293 / 418 page

Preliminary

DS41364A-page 291

PIC16F193X/LF193X

22.5.2

SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPSTAT register is cleared.

The received address is loaded into the SSPBUF reg-

ister and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF bit of the SSPSTAT

ister is set. The BOEN bit of the SSPCON3 register

modifies this operation. For more information see

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPIF, must be cleared by software.

When the SEN bit of the SSPCON2 register is set, SCL

will be held low (clock stretch) following each received

byte. The clock must be released by setting the CKP

bit of the SSPCON1 register, except sometimes in

10-bit mode. See Section 22.3.5 “Master Mode” for

more detail.

22.5.2.1

7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSP module configured as an I2C Slave in

7-bit Addressing mode. All decisions made by hard-

ware or software and their effect on reception.

Figure 22-10 and Figure 22-11 is used as a visual

reference for this description.

This is a step by step process of what typically must

be done to accomplish I2C communication.

Start bit detected.

S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

Matching address with R/W bit clear is received.

The slave pulls SDA low sending an ACK to the

master, and sets SSPIF bit.

Software clears the SSPIF bit.

Software reads received address from SSPBUF

clearing the BF flag.

If SEN = 1; Slave software sets CKP bit to

release the SCL line.

The master clocks out a data byte.

Slave drives SDA low sending an ACK to the

master, and sets SSPIF bit.

10. Software clears SSPIF.

11. Software reads the received byte from SSPBUF

clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit of

SSPSTAT, and the bus goes idle.

22.5.2.2

7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCL. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I2C commun-

cation. Figure 22-12 displays a module using both

address and data holding. Figure 22-13 includes the

operation with the SEN bit of the SSPCON2 register

set.

S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

Matching address with R/W bit clear is clocked

in. SSPIF is set and CKP cleared after the 8th

falling edge of SCL.

Slave clears the SSPIF.

Slave can look at the ACKTIM bit of the

SSPCON3 register to determine if the SSPIF

was after or before the ACK.

Slave reads the address value from SSPBUF,

clearing the BF flag.

Slave sets ACK value clocked out to the master

by setting ACKDT.

Slave releases the clock by setting CKP.

SSPIF is set after an ACK, not after a NACK.

If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPIF.

11. SSPIF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit of SSPCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

Note: SSPIF is still set after the 9th falling edge of

SCL even if there is no clock stretching and

BF has been cleared. Only if NACK is sent to

Master is SSPIF not set

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