PIC16F1933-ESLASHP datasheet(110/418 Pages) MICROCHIP

110 / 418 page

PIC16F193X/LF193X

DS41364A-page 108

Preliminary

8.2

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 8-1)

controls the system clock and frequency selection

options. The OSCCON register contains the following

bits:

• Frequency selection bits (IRCF)

• System clock select bits (SCS)

• Software PLL enable bit (SPLLEN)

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0

R/W-1/1

U-0

R/W-0/0

SPLLEN

IRCF3

IRCF2

IRCF1

IRCF0

—

SCS1

SCS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

SPLLEN: Software PLL Enable bit

If PLLEN = 1:

SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN = 0:

= 4x PLL Is enabled

0 = 4x PLL is disabled

bit 6-3

IRCF<3:0>: Internal Oscillator Frequency Select bits

000x

=31 kHz LF

0010

= 31.25 kHz MF

0011

= 31.25 kHz HF(2)

0100

= 62.5 kHz MF

0101

= 125 kHz MF

0110

= 250 kHz MF

0111

= 500 kHz MF (default upon Reset)

1000

= 125 kHz HF(2)

1001

= 250 kHz HF(2)

1010

= 500 kHz HF(2)

1011

=1 MHz HF

1100

=2 MHz HF

1101

=4 MHz HF

1110

=8 MHz HF

1111

= 16 MHz HF

bit 2

Unimplemented: Read as ‘0’

bit 1-0

SCS<1:0>: System Clock Select bits

= Internal oscillator block

= Timer1 oscillator

= Clock determined by CONFIG1[FOSC<2:0>].

Note

Reset state depends on state of the IESO Configuration bit.

Duplicate frequency derived from HFINTOSC.

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