PIC16F1933-ESLASHP datasheet(123/418 Pages) MICROCHIP

123 / 418 page

Preliminary

DS41364A-page 121

PIC16F193X/LF193X

9.0

SR LATCH

The module consists of a single SR Latch with multiple

Set and Reset inputs as well as separate latch outputs.

The SR Latch module includes the following features:

• Programmable input selection

• SR Latch output is available internally/externally

• Separate Q and Q outputs

• Firmware Set and Reset

9.1

Latch Operation

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. The latch can be Set or Reset by CxOUT,

SRI pin, or variable clock. Additionally the SRPS and the

SRPR bits of the SRCON0 register may be used to Set

or Reset the SR Latch, respectively. The latch is

Reset-dominant, therefore, if both Set and Reset inputs

are high the latch will go to the Reset state. Both the

SRPS and SRPR bits are self resetting which means

that a single write to either of the bits is all that is

necessary to complete a latch Set or Reset operation.

9.2

Latch Output

The SRQEN and SRNQEN bits of the SRCON0 regis-

ter control the Q and Q latch outputs. Both of the SR

latch outputs may be directly output to an I/O pin at the

same time.

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

9.3

Effects of a Reset

Upon any device Reset, the SR latch is not initialized.

The user’s firmware is responsible to initialize the latch

output before enabling it to the output pins.

FIGURE 9-1:

SR LATCH SIMPLIFIED BLOCK DIAGRAM

SRPS

Note

If R = 1 and S = 1 simultaneously, Q = 0, Q = 1

Pulse generator causes a 1 Q-state pulse width.

Name denotes the connection point at the comparator output.

Pulse

Gen(2)

Latch(1)

SRQEN

SRSPE

SRSC2E

SRSCKE

SRCLK

SYNCC2OUT(3)

SRSC1E

SYNCC1OUT(3)

SRPR

Pulse

Gen(2)

SRRPE

SRRC2E

SRRCKE

SRCLK

SYNCC2OUT(3)

SRRC1E

SYNCC1OUT(3)

SRLEN

SRNQEN

SRLEN

SRQ

SRNQ

SRI

PIC16F1933-E/P Datasheet(PDF) 123 Page - Microchip Technology

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