SPMCK16Z4MPV20 datasheet(293/500 Pages) FREESCALE

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M68HC16 Z SERIES

ELECTRICAL CHARACTERISTICS

USER’S MANUAL

A-9

Table A-10 25.17-MHz Clock Control Timing

(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)

Num

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range1

MC68HC16Z1

MC68HC16Z2

MC68HC16Z3

NOTES:

1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires

a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the

MC68HC16Z3 requires a 4.194 MHz crystal reference.

fref

3.2

5.2

kHz

MHz

System Frequency2

On-Chip PLL System Frequency

Slow On-Chip PLL System Frequency

Fast On-Chip PLL System Frequency

External Clock Operation

2. All internal registers retain data at 0 Hz.

fsys

4 (fref)

4 (fref) /128

25.17

MHz

PLL Lock Time1, 7, 8, 9

Changing W or Y in SYNCR or exiting from

LPSTOP3

Warm Start-Up4

Cold Start-Up (fast reference option only)5

3. Assumes that VDDSYN and VDD are stable, that an external filter is attached to the XFC pin, and that the crystal

oscillator is stable.

4. Assumes that VDDSYN is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator

is stable, followed by VDD ramp-up. Lock time is measured from VDD at specified minimum to RESET negated.

5. Cold start is measured from VDDSYN and VDD at specified minimum to RESET negated.

tlpll

—

VCO Frequency6

6. Internal VCO frequency (fVCO) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-

vide-by-two circuit that is not in the synthesizer feedback loop.

When X = 0, the divider is enabled, and fsys = fVCO ÷ 4.

When X = 1, the divider is disabled, and fsys = fVCO ÷ 2.

X must equal one when operating at maximum specified fsys.

fVCO

—

2 (fsys max)

MHz

Limp Mode Clock Frequency

SYNCR X bit = 0

SYNCR X bit = 1

flimp

—

fsys max/2

fsys max

MHz

CLKOUT Jitter1, 7, 8, 9, 10

Short term (5

µs interval)

Long term (500

µs interval)

7. This parameter is periodically sampled rather than 100% tested.

8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total

external resistance from the XFC pin due to external leakage must be greater than 15 M

Ω to guarantee this

specification. Filter network geometry can vary depending upon operating environment

9. Proper layout procedures must be followed to achieve specifications.

10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-

mum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-

nal clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator

frequency increase the Jclk percentage for a given interval. When jitter is a critical constraint on control system

operation, this parameter should be measured during functional testing of the final system.

clk

–1.0

–0.05

1.0

0.5

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