SPMCK16Z4MPV20 datasheet(34/500 Pages) FREESCALE

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NOMENCLATURE

M68HC16 Z SERIES

2-6

USER’S MANUAL

2.4 Conventions

Logic level one is the voltage that corresponds to a Boolean true (1) state.

Logic level zero is the voltage that corresponds to a Boolean false (0) state.

Set refers specifically to establishing logic level one on a bit or bits.

Clear refers specifically to establishing logic level zero on a bit or bits.

Asserted means that a signal is in active logic state. An active low signal changes

from logic level one to logic level zero when asserted, and an active high signal chang-

es from logic level zero to logic level one.

Negated means that an asserted signal changes logic state. An active low signal

changes from logic level zero to logic level one when negated, and an active high sig-

nal changes from logic level one to logic level zero.

A specific mnemonic within a range is referred to by mnemonic and number. A15 is

bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select op-

tion register 0. A range of mnemonics is referred to by mnemonic and the numbers

that define the range. VBR[4:0] are bits four to zero of the vector base register;

CSOR[0:5] are the first six chip-select option registers.

Parentheses are used to indicate the content of a register or memory location, rather

than the register or memory location itself. For example, (A) is the content of accumu-

lator A. (M

: M + 1) is the content of the word at address M.

LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-

ences to low and high bytes are spelled out.

LSW means least significant word or words. MSW means most significant word or

words.

ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus.

DATA is the data bus. DATA[15:8] are the eight MSB of the data bus.

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SPMCK16Z4MPV20 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc