SPMCK16Z4MPV20 datasheet(99/500 Pages) FREESCALE

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M68HC16 Z SERIES

CENTRAL PROCESSING UNIT

USER’S MANUAL

4-39

4.13.3 Exception Processing Sequence

Exception processing is performed in four phases. Priority of all pending exceptions is

evaluated and the highest priority exception is processed first. Processor state is

stacked, then the CCR PK extension field is cleared. An exception vector number is

acquired and converted to a vector address. The content of the vector address is load-

ed into the PC and the processor jumps to the exception handler routine.

There are variations within each phase for differing types of exceptions. However, all

vectors except RESET are 16-bit addresses, and the PK field is cleared during excep-

tion processing. Consequently, exception handlers must be located within bank 0 or

vectors must point to a jump table in bank 0.

4.13.4 Types of Exceptions

Exceptions can be either internally or externally generated. External exceptions, which

are defined as asynchronous, include interrupts, bus errors, breakpoints, and resets.

Internal exceptions, which are defined as synchronous, include the software interrupt

(SWI) instruction, the background (BGND) instruction, illegal instruction exceptions,

and the divide-by-zero exception.

4.13.4.1 Asynchronous Exceptions

Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but excep-

tion processing is synchronized. For all asynchronous exceptions except RESET, ex-

ception processing begins at the first instruction boundary following recognition of an

exception. Refer to 5.8.1 Interrupt Exception Processing for more information con-

cerning asynchronous exceptions.

Because of pipelining, the stacked return PK : PC value for all asynchronous excep-

tions, other than reset, is equal to the address of the next instruction in the current in-

struction stream plus $0006. The RTI instruction, which must terminate all exception

handler routines, subtracts $0006 from the stacked value to resume execution of the

interrupted instruction stream.

4.13.4.2 Synchronous Exceptions

Synchronous exception processing is part of an instruction definition. Exception pro-

cessing for synchronous exceptions is always completed, and the first instruction of

the handler routine is always executed, before interrupts are detected.

Because of pipelining, the value of PK : PC at the time a synchronous exception exe-

cutes is equal to the address of the instruction that causes the exception plus $0006.

Because RTI always subtracts $0006 upon return, the stacked PK : PC must be ad-

justed by the instruction that caused the exception so that execution resumes with the

following instruction. For this reason, $0002 is added to the PK : PC value before it is

stacked.

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