SPMCK16Z4MPV20 datasheet(49/500 Pages) FREESCALE

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M68HC16 Z SERIES

OVERVIEW

USER’S MANUAL

3-15

Table 3-5 M68HC16 Z-Series Signal Function

Mnemonic

Signal Name

Function

ADDR[19:0]

Address Bus

20-bit address bus used by CPU16

AN[7:0]

ADC Analog Input

Inputs to ADC multiplexer

Address Strobe

Indicates that a valid address is on the address bus

AVEC

Autovector

Requests an automatic vector during interrupt acknowledge

BERR

Bus Error

Indicates that a bus error has occurred

Bus Grant

Indicates that the MCU has relinquished the bus

BGACK

Bus Grant

Acknowledge

Indicates that an external device has assumed bus mastership

BKPT

Breakpoint

Signals a hardware breakpoint to the CPU

Bus Request

Indicates that an external device requires bus mastership

CLKOUT

System Clockout

System clock output

CS[10:0]

Chip-Selects

Select external devices at programmed addresses

CSBOOT

Boot Chip Select

Chip select for external boot start-up ROM

DATA[15:0]

Data Bus

16-bit data bus

Data Strobe

During a read cycle, indicates that an external device should

place valid data on the data bus. During a write cycle, indicates

that valid data is on the data bus.

DSACK[1:0]

Data and Size

Acknowledge

Provide asynchronous data transfers and dynamic bus sizing

DSI, DSO,

DSCLK

Development Serial In,

Out, Clock

Serial I/O and clock for background debug mode

EXTAL, XTAL

Crystal Oscillator

Connections for clock synthesizer circuit reference a crystal or

an external oscillator can be used

FC[2:0]

Function Codes

Identify processor state and current address space

FREEZE

Freeze

Indicates that the CPU has entered background mode

HALT

Halt

Suspend external bus activity

IRQ[7:1]

Interrupt Request Level

Provides an interrupt priority level to the CPU

IPIPE[1:0]

Instruction Pipeline

Indicate instruction pipeline activity

MISO

Master In Slave Out

Serial input to QSPI in master mode; serial output from QSPI in

slave mode

MISO1

Master In Slave Out

Serial input to SPI in master mode; serial output from SPI in

slave mode

MODCLK

Clock Mode Select

Selects the source and type of system clock

MOSI

Master Out Slave In

Serial output from QSPI in master mode; serial input to QSPI in

slave mode

MOSI1

Master Out Slave In

Serial output from SPI in master mode; serial input to SPI in

slave mode

PADA[7:0]

Port ADA

ADC digital input port signals

PAI

Pulse Accumulator Input

Input to the GPT pulse accumulator

PCLK

Auxiliary Timer Clock

GPT external clock input

PC[6:0]

Port C

Port C digital output port signals

PCS[3:0]

Peripheral Chip Select

QSPI peripheral chip-selects

PE[7:0]

Port E

Port E digital I/O port signals

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SPMCK16Z4MPV20 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc

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