SPMCK16Z4MPV20 datasheet(65/500 Pages) FREESCALE

65 / 500 page

M68HC16 Z SERIES

CENTRAL PROCESSOR UNIT

USER’S MANUAL

4-5

SM — Saturate Mode Bit

When SM is set and either EV or MV is set, data read from AM using TMER or TMET

is given maximum positive or negative value, depending on the state of the AM sign

bit before overflow.

PK[3:0] — Program Counter Address Extension Field

This field is concatenated with the program counter to form a 20-bit address.

4.2.6 Address Extension Register and Address Extension Fields

There are six 4-bit address extension fields. EK, XK, YK, and ZK are contained by the

address extension register (K), PK is part of the CCR, and SK stands alone.

Extension fields are the bank portions of 20-bit concatenated bank:byte addresses

used in the CPU16 linear memory management scheme.

All extension fields except EK correspond directly to a register. XK, YK, and ZK extend

registers IX, IY, and IZ. PK extends the PC; and SK extends the SP. EK holds the four

MSB of the 20-bit address used by the extended addressing mode.

4.2.7 Multiply and Accumulate Registers

The multiply and accumulate (MAC) registers are part of a CPU submodule that per-

forms repetitive signed fractional multiplication and stores the cumulative result. These

operations are part of control-oriented digital signal processing.

There are four MAC registers. Register H contains the 16-bit signed fractional multipli-

er. Register I contains the 16-bit signed fractional multiplicand. Accumulator M is a

specialized 36-bit product accumulation register. XMSK and YMSK contain 8-bit mask

values used in modulo addressing.

The CPU16 has a special subset of signal processing instructions that manipulate the

MAC registers and perform signal processing calculations.

4.3 Memory Management

The CPU16 provides a 1-Mbyte address space. There are 16 banks within the address

space. Each bank is made up of 64 Kbytes addressed from $0000 to $FFFF. Banks

are selected by means of the address extension fields associated with individual

CPU16 registers.

In addition, address space can be split into discrete 1-Mbyte program and data spaces

by externally decoding the MCU’s function code outputs. When this technique is used,

instruction fetches and reset vector fetches access program space, while exception

vector fetches (other than for reset), data accesses, and stack accesses are made in

data space.

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SPMCK16Z4MPV20 Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc