SPMCK16Z4MPV20 datasheet(69/500 Pages) FREESCALE

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M68HC16 Z SERIES

CENTRAL PROCESSOR UNIT

USER’S MANUAL

4-9

All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an

operand or an extension field to form a 20-bit effective address.

NOTE

Access across 64-Kbyte address boundaries is transparent. AD-

DR[19:16] of the effective address are changed to make an access

across a bank boundary. Extension field values will not change as a

result of effective address computation.

4.6.1 Immediate Addressing Modes

In the immediate modes, an argument is contained in a byte or word immediately fol-

lowing the instruction. For IMM8 and IMM16 modes, the effective address is the ad-

dress of the argument.

There are three specialized forms of IMM8 addressing.

• The AIS, AIX, AIY, AIZ, ADDD, and ADDE instructions decrease execution time

by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an ap-

propriate register.

• The MAC and RMAC instructions use an 8-bit immediate operand to specify two

signed 4-bit index register offsets.

• The PSHM and PULM instructions use an 8-bit immediate mask operand to indi-

cate which registers must be pushed to or pulled from the stack.

Table 4-1 Addressing Modes

Mode

Mnemonic

Description

Accumulator Offset

E,X

Index register X with accumulator E offset

E,Y

Index register Y with accumulator E offset

E,Z

Index register Z with accumulator E offset

Extended

EXT

Extended

EXT20

20-bit extended

Immediate

IMM8

8-bit immediate

IMM16

16-bit immediate

Indexed 8-Bit

IND8, X

Index register X with unsigned 8-bit offset

IND8, Y

Index register Y with unsigned 8-bit offset

IND8, Z

Index register Z with unsigned 8-bit offset

Indexed 16-Bit

IND16, X

Index register X with signed 16-bit offset

IND16, Y

Index register Y with signed 16-bit offset

IND16, Z

Index register Z with signed 16-bit offset

Indexed 20-Bit

IND20, X

Index register X with signed 20-bit offset

IND20, Y

Index register Y with signed 20-bit offset

IND20, Z

Index register Z with signed 20-bit offset

Inherent

INH

Inherent

Post-Modified Index

IXP

Signed 8-bit offset added to index register

X after effective address is used

Relative

REL8

8-bit relative

REL16

16-bit relative

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