SPMCK16Z4MPV20 datasheet(98/500 Pages) FREESCALE

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CENTRAL PROCESSING UNIT

M68HC16 Z SERIES

4-38

USER’S MANUAL

4.13.2 Exception Stack Frame

During exception processing, the contents of the program counter and condition code

ception processing, the stacked PK : PC value is the address of the next instruction in

the current instruction stream, plus $0006. Figure 4-6 shows the exception stack

frame.

Figure 4-6 Exception Stack Frame Format

Table 4-5 Exception Vector Table

Vector

Number

Vector

Address

Space

Type of

Exception

0000

Reset — Initial ZK, SK, and PK

0002

Reset — Initial PC

0004

Reset — Initial SP

0006

Reset — Initial IZ (Direct Page)

0008

Breakpoint

000A

Bus Error

000C

Software Interrupt

000E

Illegal Instruction

0010

Division by Zero

9 – E

0012 – 001C

Unassigned, Reserved

001E

Uninitialized Interrupt

0020

Unassigned, Reserved

0022

Level 1 Interrupt Autovector

0024

Level 2 Interrupt Autovector

0026

Level 3 Interrupt Autovector

0028

Level 4 Interrupt Autovector

002A

Level 5 Interrupt Autovector

002C

Level 6 Interrupt Autovector

002E

Level 7 Interrupt Autovector

0030

Spurious Interrupt

19 – 37

0032 – 006E

Unassigned, Reserved

38 – FF

0070 – 01FE

User-Defined Interrupts

Low Address

⇐ SP After Exception Stacking

Condition Code Register

High Address

Program Counter

⇐ SP Before Exception Stacking

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