SPMCK16Z4MPV20 datasheet(327/500 Pages) FREESCALE

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M68HC16 Z SERIES

ELECTRICAL CHARACTERISTICS

USER’S MANUAL

A-43

Table A-26 25.17-MHz ECLK Bus Timing

and V

DDSYN

= 5.0 Vdc

± 5%, V

= 0 Vdc, T

= T

to T

NOTES:

1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted.

Num

Characteristic

Symbol

Min

Max

Unit

ECLK Low to Address Valid2

2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.

tEAD

—40

ECLK Low to Address Hold

tEAH

—

ECLK Low to CS Valid (CS Delay)

tECSD

—

100

ECLK Low to CS Hold

tECSH

—

CS Negated Width

tECSN

—

Read Data Setup Time

tEDSR

—

Read Data Hold Time

tEDHR

5—

ECLK Low to Data High Impedance

tEDHZ

—40

CS Negated to Data Hold (Read)

tECDH

0—

E10

CS Negated to Data High Impedance

tECDZ

—1

tcyc

E11

ECLK Low to Data Valid (Write)

tEDDW

—2

tcyc

E12

ECLK Low to Data Hold (Write)

tEDHW

5—

E13

CS Negated to Data Hold (Write)

tECHW

0—

E14

Address Access Time (Read)3

3. Address access time = tEcyc – tEAD – tEDSR.

tEACC

255

—

E15

Chip-Select Access Time (Read)4

4. Chip select access time = tEcyc – tECSD – tEDSR.

tEACS

195

—

E16

Address Setup Time

tEAS

—

1/2

tcyc

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SPMCK16Z4MPV20 Datasheet(PDF) 327 Page - Freescale Semiconductor, Inc

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