SPMCK16Z4MPV20 datasheet(486/500 Pages) FREESCALE

486 / 500 page

M68HC16 Z SERIES

I-4

USER’S MANUAL

–D–

DAC capacitor array (CDAC) 8-22

DATA 5-31

Data

and size acknowledge (DSACK).

See DSACK 5-24

bus

mode selection 5-50

signals (DATA) 5-31

frame 9-25, 10-17

multiplexer 5-35

strobe (DS).

See DS 5-31

DATA (definition) 2-6

DC characteristics

16.78 MHz A-12

20.97 MHz A-14

25.17 MHz A-16

low voltage, 16.78 MHz A-10

DDRE 5-70, D-9

DDRF 5-70, D-11

DDRGP 11-8, 11-14, D-69

DDRM D-58

DDRQS 9-4, 9-16, 9-20, D-45

Delay

after transfer (DT) 9-18, D-53

before SCK (DSCKL) D-49

Designated CPU space 5-32

Design-Net database B-8

Development

support for CPU16 4-40

tools and support C-1

Digital

control subsystem 8-6

signal processing (DSP) 4-45

Divider/counter 5-6

Double

-buffered 9-27, 9-28, 10-19, 10-20

bus fault 5-45

DREG D-22

Driver types 3-12

DS 4-41, 5-31, 5-37, 5-40, 5-45, 5-47, 5-51

DSACK 5-24, 5-32, 5-37, 5-41, 5-43, 5-54, 5-60, 5-65,

5-66, 5-67, 5-68

external/internal generation 5-40

option fields 5-40

signal effects 5-34

source specification in asynchronous mode 5-66,

D-19

DSCK D-53

DSCKL D-49

DSCLK 4-44, 5-53

DSI 5-53

DSO 5-53

DSP 4-45

DT D-53

DTL D-49

Dynamic bus sizing 5-33

–E–

EBI 5-60

ECLK 5-21

bus timing

16.78 MHz A-41

20.97 MHz A-42

25.17 MHz A-43

low voltage A-40

output timing diagram A-28

timing diagram A-44

EDGE D-72

Edge-detection logic 11-12

EDGExA/B 11-12

EDIV 5-21, D-8

EK 4-5

Electrical characteristics A-1

EMUL D-26

Emulation mode control (EMUL) D-26

Ending queue pointer (ENDQP) D-50

ENDQP 9-8, D-50

EQUATES.ASM E-2

Error

conditions 9-28, 10-21

detection circuitry 9-2

EV 4-4

Event counting mode 11-15

Exception

asynchronous 4-39

definition 4-37

multiple 4-40

processing 5-48

sequence 4-39

stack frame 4-38

format 4-38

synchronous 4-39

types 4-39

vector 4-37, 5-48

table 4-38

Execution

process 4-36

unit 4-35

EXOFF D-6

EXT D-8

EXTAL 5-5, 5-56

Extended addressing modes 4-10

Extension

bit overflow flag (EV) 4-4

field (SK) 4-3

fields 4-6

External

bus

arbitration 5-46

clock

division bit (EDIV) 5-21, D-8

operation during LPSTOP 5-21

signal (ECLK) 5-21

interface (EBI) 5-29

control signals 5-31

circuit settling time 8-23

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 486 Page - Freescale Semiconductor, Inc

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