SPMCK16Z4MPV20 datasheet(110/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-4

USER’S MANUAL

5.3 System Clock

The system clock in the SIM provides timing signals for the IMB modules and for an

external peripheral bus. Because the MCU is a fully static design, register and memory

contents are not affected when the clock rate changes. System hardware and software

support changes in clock rate during operation.

The system clock signal can be generated from one of three sources. An internal

phase-locked loop (PLL) can synthesize the clock from a fast reference, a slow refer-

ence, or the clock signal can be directly input from an external frequency source.

NOTE

Whether the PLL can use a fast or slow reference is determined by

the device. A particular device cannot use both a fast and slow refer-

ence.

The fast reference is typically a 4.194-MHz crystal; the slow reference is typically a

32.768-kHz crystal. Each reference frequency may be generated by sources other

than a crystal. Keep these sources in mind while reading the rest of this section.

Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for clock specifications.

Figure 5-2 is a block diagram of the clock submodule.

Figure 5-2 System Clock Block Diagram

Z SERIES PLL BLOCK

PHASE

COMPARATOR

LOW-PASS

FILTER

VCO

CRYSTAL

OSCILLATOR

SYSTEM

CLOCK

SYSTEM CLOCK CONTROL

FEEDBACK DIVIDER

EXTAL

XTAL

XFC

CLKOUT

1281

MODCLK

VDDSYN

NOTES:

÷ 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR.

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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