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DM3725 Datasheet(PDF) 52 Page - Texas Instruments

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Part # DM3725
Description  Applications Processor
PDF  268 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725 Datasheet(HTML) 52 Page - Texas Instruments

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DM3730, DM3725
SPRS685 – AUGUST 2010
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)
BALL
BALL TOP
PIN NAME [3]
MODE [4]
TYPE [5]
BALL
BALL RESET RESET
POWER [9] HYS [10]
BUFFER
PULLUP
IO CELL
BOTTOM
[2]
RESET
REL. STATE
REL. MODE
STRENGTH /DOWN
[13]
[1]
STATE [6]
[7]
[8]
(mA) [11]
TYPE [12]
gpio_179
4
IO
safe_mode
7
-
U8
NA
mcspi2_somi
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpt_10_pwm_evt
1
IO
hsusb2_data5
3
IO
gpio_180
4
IO
safe_mode
7
-
W10
NA
mmc2_clk
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi3_clk
1
IO
gpio_130
4
IO
safe_mode
7
-
R10
NA
mmc2_cmd
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi3_simo
1
IO
gpio_131
4
IO
safe_mode
7
-
T10
NA
mmc2_dat0
0
IO
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi3_somi
1
IO
gpio_132
4
IO
safe_mode
7
-
T9
NA
mmc2_dat1
0
IO
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_133
4
IO
safe_mode
7
-
U10
NA
mmc2_dat2
0
IO
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi3_cs1
1
O
gpio_134
4
IO
safe_mode
7
-
U9
NA
mmc2_dat3
0
IO
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi3_cs0
1
IO
gpio_135
4
IO
safe_mode
7
-
V10
NA
mmc2_dat4
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_dir_dat0
1
O
mmc3_dat0
3
IO
gpio_136
4
IO
safe_mode
7
-
R2
NA
uart1_rts
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_149
4
IO
safe_mode
7
-
H3
NA
uart1_rx
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp1_clkr
2
IO
mcspi4_clk
3
IO
gpio_151
4
IO
safe_mode
7
-
L4
NA
uart1_tx
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_148
4
IO
safe_mode
7
-
Y24
NA
uart2_cts
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dx
1
IO
gpt_9_pwm_evt
2
IO
gpio_144
4
IO
safe_mode
7
-
AA24
NA
uart2_rts
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dr
1
I
gpt_10_pwm_evt
2
IO
gpio_145
4
IO
52
TERMINAL DESCRIPTION
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): DM3730 DM3725



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