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DM3725 Datasheet(PDF) 24 Page - Texas Instruments |
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DM3725 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 268 page  DM3730, DM3725 SPRS685 – AUGUST 2010 www.ti.com 11. BUFFER STRENGTH: Drive strength of the associated output buffer. 12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. Note: The pullup/pulldown drive strength is equal to minimum = 50mA, typical = 100 mA, maximum = 250 mA (unless otherwise specified), except for CBP balls P27, P26, R27, and R25, and CUS balls N22 and P24, which the pulldown drive strength is equal to 1.8 k Ω. 13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. NOTE In the DM3730/25 device, new Far End load Settings registers are added for some IOs. This new feature configures the IO according to the transmission line and the application/peripheral load. For a full description on these registers, see the System Control Module / SCM Functional Description / Functional Register Description / Signal Integrity Parameter Control Registers with Pad Group Assignment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Table 2-1. Ball Characteristics (CBP Pkg.)(3) BALL BUFFER BALL BALL RESET PULLUP BALL TOP RESET STRENG IO CELL BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN [2] REL. TH (mA) [13] [1] STATE [6] [8] TYPE [12] STATE [7] [11] NA J2 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA J1 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA G2 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA G1 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA F2 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA F1 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA D2 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA D1 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B13 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A13 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B14 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A14 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B16 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A16 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B19 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A19 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B3 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A3 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B5 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A5 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B8 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A8 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B9 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A9 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA B21 sdrc_d24 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA A21 sdrc_d25 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA D22 sdrc_d26 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA D23 sdrc_d27 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA E22 sdrc_d28 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA E23 sdrc_d29 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA G22 sdrc_d30 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS NA G23 sdrc_d31 0 IO L Z 0 vdds_mem Yes 4 (10) PU/ PD LVCMOS 24 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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