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DM3725 Datasheet(PDF) 63 Page - Texas Instruments |
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DM3725 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 268 page  DM3730, DM3725 www.ti.com SPRS685 – AUGUST 2010 (1) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior. (3) PU = [50 to 100 k Ω] per default or [10 to 50 kΩ] according to the selected mode. For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). PD: 30 to 150 k Ω. (4) These signals are feed-through balls. For more information, see Table 2-27. (5) NA in this table stands for "Not Applicable". (6) In the safe_mode_out1, the buffer is configured to drive 1. (7) Depending on the sys_clkreq direction the corresponding reset released state value can be: – Z if sys_clkreq is used as input – 1 if sys_clkreq is used as output For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (8) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (9) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described as follows: Nominal resistance = 1.66 k Ω in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load range of 5 pF to 15 pF. (10) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1, CONTROL_PROG_IO_WKUP1 control modules in the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application. (11) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application. (12) Mux0 if sys_boot6 is pulled down (clock master). Table 2-3. Ball Characteristics (CUS Pkg.)(1) BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN [7] (mA) [11] TYPE [12] D7 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C5 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C6 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B5 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS D9 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS D10 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C7 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B7 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B11 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C12 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B12 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS D13 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C13 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B14 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS A14 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B15 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C9 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS E12 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B8 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B9 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C10 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS B10 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS D12 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS E13 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 63 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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