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DM3725 Datasheet(PDF) 142 Page - Texas Instruments |
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DM3725 Datasheet(HTML) 142 Page - Texas Instruments |
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142 / 268 page  DM3730, DM3725 SPRS685 – AUGUST 2010 www.ti.com (1) At ball level. (2) These values are defined when the SmartReflexTM feature is deactivated. They can be lower when SmartReflex is activated. (3) Minimum OPP voltage values defined in this table include any voltage transient. (4) OPP130 is not available above TJ of 90C. Table 4-19. Processor Voltages With SmartReflexTM RETENTIO OPP50 OPP100 OPP130(5) OPP1G (5) (6) N MIN MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX VDD1(1) (2) 0.8 0.92 0.97 1.02 1.08 1.14 1.2 1.21 1.27 1.33 1.28 1.33 1.38 (3) (4) (V) (1) At ball level. (2) This table defines the safe VDD1 (vdd_mpu_iva) voltage ranges to be used before using the SmartReflex AVS feature for OPPs calibration. (3) These VDD1 (vdd_mpu_iva) values are the required voltage ranges prior to enabling the SmartReflex AVS feature. After calibration, the minimum voltage may be lower than this specification. (4) Minimum OPP voltage values defined in this table include any voltage transient. (5) OPP130 and OPP1G are not available above TJ of 90C. (6) OPP1G is a high performance operating point which has following requirements: – ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1mF capacitor connected to cap_vdd_bb_mpu_iva. – AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage. Table 4-20. Processor Clocks OPP50 OPP100 OPP130 OPP1G (2) Description Source Clock Max Ratio Max Ratio Max Ratio Max Ratio Freq.(MHz) Freq.(MHz) Freq.(MHz) Freq.(MHz) DPLL1 - 1200 - 1200 - 1600 - 2000 - Locked Frequency DPLL1CLKO DPLL1 300 2 *(M2 = 2)(1) 600 2 *(M2 = 1)(1) 800 2 *(M2 = 1)(1) 1000 2 *(M2 = 1)(1) UT_M2 Locked Frequency DPLL2 - 1040 - 1040 - 1320 - 1600 - Locked Frequency DPLL2CLKO DPLL2 260 2 *(M2 = 2)(1) 520 2 *(M2 = 2)(1) 660 2 *(M2 = 2)(1) 800 2 *(M2 = 2)(1) UT_M2 Locked Frequency ARM_FCLK DPLL1CLKO 300 1 600 1 800 1 1000 1 UT_M2 IVA_CLK DPLL2CLKO 260 1 520 1 660 1 800 1 UT_M2 (1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). (2) OPP1G is a high performance operating point which has following requirements: – ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1mF capacitor connected to cap_vdd_bb_mpu_iva. – AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage. 142 Clock Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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